Embedded Systems & Software

Electronic alarm clock on FPGA, Nios II co-design

FPGA

Co-design HW/SW

Nios II

Langage C

Quartus / Qsys

Hardware and software co-design of a complete alarm clock on a DE10-Lite FPGA, with a Nios II processor programmed in C and driven by interrupts. First-year Master's mini-project in MESI.

Nios II processor: 50 MHz
melodies instead of a beep: 8

Read the report (PDF)

ContextHW/SW co-design, DE10-Lite

ApproachNios II in C, interrupts

ResultComplete clock, 8 melodies

Context

Embedded Digital Systems mini-project in the first-year Master's MESI, supervised by Mr F. Dadouche. The task was to design the hardware and software of a system on chip together. The target was a DE10-Lite board (Intel MAX 10 FPGA) to be turned into an alarm clock.

What I did

A system on chip in Quartus and Platform Designer, Nios II at 50 MHz and two timers.
Displays, switches, buttons, LEDs and speaker connected through PIOs sized to the bit.
Software in C, a main loop and two interrupt routines (time base, sound).
Beyond the specification, I added a 12h/24h mode, 8 melodies, two setting modes, locking and the compile time.

What I noticed and learned

In embedded systems, every byte counts. Without sscanf, I decoded the compile time by hand.
Variables shared with interrupts are protected by critical sections.

My mistakes

I first coded the alarm in one block, relying too much on examples and on AI, with bugs that were hard to isolate. On my supervisor's advice, I switched to incremental development.

Results

A fully working alarm clock, validated function by function on the board.
I met the whole specification and added five improvements.

Tech stack

Quartus Prime

Platform Designer (Qsys)

Nios II (SoPC)